The design and development of integrated circuits (ICs) involves extensive testing to ensure that the ICs function correctly. It is common for an IC to include many millions of individual transistors configured in various logical arrangements using interconnect wires. As new semiconductor manufacturing processes are developed, the physical sizes of the transistors are continually shrinking. For example, transistor gate lengths of 65 nanometers or smaller are becoming common. Furthermore, as each new semiconductor manufacturing process reduces feature sizes, transistor usage per IC die increases. Also, the cross-sections of the interconnect wires are reduced. In spite of the reduction in magnitude of typical operation current for an IC, the current density on the interconnect wires has increased. As such, the interconnect wires are at risk of being damaged.
There are some situations where the risk of damage to the interconnect wires is even greater. One such situation occurs when power is first applied to an IC. Some circuits may enter states that were not anticipated during design, causing other circuits to contend with one another. The current caused by such contending circuits is referred to as “contention current.” Reduction or elimination of contention current is typically not considered during design of the IC. Such contention current, however, should be identified and controlled in order to reduce the risk of damage to the interconnect wires. Accordingly, there exists a need in the art for a method and apparatus for analyzing current, such as contention current, in an integrated circuit under test.